Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, medical, automobile, and other applications. The technology used to manufacture image sensors, and in particular CMOS image sensors, has continued to advance at great pace. For example, the demands of higher resolution and lower power consumption have encouraged the further miniaturization and integration of the image sensor.
A typical image sensor includes a pixel array of rows and columns comprised of individual pixels. Each pixel includes a photosensitive region and a readout region. For one commonly used type of pixel (the four transistor pixel), a transfer transistor transfers the signal output by the photosensitive region to a floating diffusion. The signal is then held by the floating diffusion until it can be read out by the readout portion of the pixel.
The floating diffusion region of a pixel is an important structure. Currently, the floating diffusion region is formed as an N+ implant in a semiconductor substrate. This enables the use of standard transistors which are adjacent to this floating diffusion (such as the transfer transistor and reset transistor). The use of the N+ implant to form the floating diffusion also provides a good ohmic contact between a contact plug and the floating diffusion.
However, there have been found to be several performance issues with this type of floating diffusion. First, the N+ implant creates an amorphous region that rearranges to reform the silicon crystalline lattice during subsequent thermal steps by a process known as solid phase epitaxial (SPE) regrowth. This regrowth begins simultaneously at several different physical locations on the floating diffusion. Where the regrowth fronts meet, a stacking fault can occur. The presence of a stacking fault in the floating diffusion will result in a much higher floating diffusion junction leakage with a consequent reduction in imager performance and lower yield.
Secondly, the high N+ implant dosage gives rise to high electric fields in the floating diffusion region, which results in increased floating diffusion junction leakage. Thirdly, the N+ implant with its high concentration diffuses laterally under the adjacent gates (the transfer gate and reset gate) and degrades their off state current performance and their short L punch-through performance. This limits the device scaling of these transistors.